Semiconductor chips and their electrical connections, such as bond wires or solder bumps, are frequently encapsulated in a plastic material in order to protect the components from mechanical and environmental damage, in particular, from moisture.
In order to save time and manufacturing costs, several packages are often encapsulated in a single plastic mass by placing the packages in a mold and injecting the plastic material into the mold. This method is associated with the problem of the poor distribution of the plastic mold material throughout the mold which can lead to the formation of voids in the encapsulation of the package. This is found to be a particular problem for packages situated in the portion of the mold furthest from the inlet point. Void formation in the plastic encapsulation mass has also been found to be a problem in stacked semiconductor packages where voids have been observed to form adjacent to the side of the spacer block which faces away from the inlet point.
Various approaches have been used to try to minimize this problem. The properties of the mold material, for example, its viscosity and the particle size of the filler, have been altered and the number of rows of packages encapsulated at one time has been reduced in an attempt to reduce the occurrence of voids. However, these methods are only partially successful and are also costly.